Integrated circuits find application in many of today's consumer electronics, such as cellular phones, video cameras, portable music players, personal computing devices etc. Integrated circuits may include a combination of active devices, passive devices and their interconnections.
A common device found within an integrated circuit is semiconductor memory devices. Semiconductor memory devices are made up of a plurality of memory cells interconnected to form a memory array. Each of the memory cells being able to store one or more bits of information. In general, one basic memory cell design is duplicated numerous times to form the memory array. While the basic cell design may be modified slightly from cell to cell, for example, one cell may be a complement of an adjacent cell, the memory array is typically described according to the basic cell design.
A known type of semiconductor memory device is static random access memory (SRAM) devices. A common form of SRAM device comprises individual memory cells each made up of a combination of one or more transistors and storage capacitors. FIG. 1 illustrates the schematic view of an SRAM cell 100 known as a one transistor (1T) static random access memory (SRAM) cell. The 1T SRAM cell 100 comprises an access transistor 120 and a storage capacitor 140 for storing information. A first terminal 122 of the access transistor 120 is connected to a bit line B/L while a second terminal 124 of the access transistor is connected to a first capacitor plate 142 of the storage capacitor 140. The storage capacitor also comprises a second capacitor plate 144 which is connected to ground. The access transistor 120 further comprises a gate terminal 126 that is connected to a word line W/L. In order to access or store information in the storage capacitor, the access transistor has to be ‘switched on’ by activating both the bit line B/L and the word line W/L.
FIG. 2 is a cross-sectional view showing a known realization of the 1T SRAM cell shown in FIG. 1. FIG. 2 shows a semiconductor structure 200 comprising a substrate 202 such as a P-type body and a 1T SRAM cell 220 formed on an n-well 204 located within the substrate. The 1T SRAM cell 220 comprises an access transistor 240 and a storage capacitor 280. Shallow trench isolation (STI) structures 206 are provided in the substrate 202 to isolate the 1T SRAM cell 220 from adjacent SRAM cells or other devices.
The access transistor 240 is made up of a gate stack comprising a gate dielectric 242 and a gate electrode 244 overlying the gate dielectric 242. Sidewall spacers 246 are provided abutting the sidewalls of the gate electrode 244. A P-type bit line region 250 is formed in the n-well 204 adjacent a first edge of the gate electrode 244 distal from the storage capacitor 280. Meanwhile a P-type cell node region 260 is formed on the opposed side of the gate electrode 244 between the gate stack and the storage capacitor 280.
The storage capacitor 280 comprises a capacitor dielectric 282 formed over the n-well 204 and a first capacitor plate 284 overlying the capacitor dielectric 282. The first capacitor plate 284 may comprise polysilicon. The capacitor dielectric 282 and the first capacitor plate overlie a plate region 286 of the n-well 204 which forms the second capacitor plate of the storage capacitor 280.
As the demand for smaller electronic devices such as cell-phones, cameras, computing devices continue, there is a corresponding need for reduction in electrical device feature sizes. Accordingly, manufacturers strive to shrink the size of memory cells such as that shown in FIGS. 1 and 2 so that their packing density can be improved. Therefore, there is a demand for memory cell designs with reduced footprint and methods for fabrication of such designs.